TSI system (
Steam turbine condition monitoring and protection system)
And the ETS system (
Steam turbine crisis tripping system)
Thermal power plant is important equipment to ensure normal operation of the steam turbine and generator, is widespread in the thermal power enterprises.
In most of the current application, the two systems are independent of each other, usually by specialized TSI equipment suppliers TSI system, while the ETS system with universal PLC to build.
But in fact there is a lot of contact between two systems, the output of the TSI system is often the ETS system input.
If we can make the two systems of organic integration, not only can save cost, more can make the system structure is simplified, thus improve the reliability.
in view of the above situation, my company chooses coldwell ESAY embedded PLC
chips built the core of the ETS system control module, through the CAN field bus and my company's fieldbus TSI system to realize the organic integration, is perfectly solved the problems existing in the current ETS system.
1, the overall design EASY embedded PLC chip has two uart serial port and a CAN interface and 32 IO pin.
The chip CAN interface is already loaded coldwell company CAN application layer protocol, this is a master-slave protocol, the communication rate of 160 k.
My company's TSI system use MVCAN - 2 CAN application layer protocol is more than a main structure of the protocol, the communication rate CAN be 10 k, 125 k, 250 k and 500 k.
Because the agreement is different, the TSI system and CAN not directly use EASY embedded PLC CAN interface with the communication chip.
To solve this problem, the ETS control module is designed to double CPU structure.
Using 8-bit MCU P89V51RD2 and independent CAN controller SJA1000 extend out another CAN communication, in the communication port loading MVCAN - 2 protocol, implementation and TSI system connection.
P89V51RD2 and EASY by two pieces of IDT7202 exchange data between the embedded PLC chips.
FIFO IDT7202 is a dual port (
1024 x 9 FIFO buffers, internal RAM.
2, hardware implementation the following are the main hardware design block diagram: P89V51RD2 through signal lines connected to the address, data and writing one piece of IDT7202 written to the port, and through the address, data and read signal lines connected to another IDT7202 readout port;
Embedded PLC chip only general IO pin, no address, data, and read/write signal lines, can only use general IO to simulate the read and write operations.
Particular way is embedded PLC chip P1 mouth as an 8-bit data port, respectively, with two IDT7202 another set of read and write port connection, P3.
2 used as read, write, enabling signal, P4.
2 as a state judge signal.
With embedded PLC chip P2 mouth extends the eight relay output, other interface and features of the embedded PLC chips are designed according to typical applications.
Will P89V51RD2 uart serial port is designed for standard rs232 serial interface, when set, the serial port is used to download the TSI system configuration files, runtime loading MODBUS protocol used to communicate with PC or other equipment.
Finally completed the ETS controller has the following features: no relay output, one CAN interface with the TSI system interconnection, another CAN interface CAN be used in IO expansion and interconnection between ETS controller, COM1 serial port is used to download and PLC ladder diagram to monitor, COM2 for CAN configuration and PLC communication, COM3 (
By P89V51RD2 extension)
For TSI configuration download and TSI data monitoring.
implementation software consists of two parts.
Part is running in the software of P89V51RD2, another part is embedded in the chip embedded PLC software
run in P89V51RD2 software using C language to write.
Software is designed as two work modes: setting mode and working mode.
In setting mode, the user USES the PC via a serial port pass the TSI system configuration file to P89V51RD2, P89V51RD2 will file is stored in the internal FLASH;
Under the working pattern, P89V51RD2 according to the configuration file parsing by the SJA1000 receives the TSI system data, and the data according to certain format by IDT7202 transmission to the embedded PLC.
At the same time, data from all parts of the embedded PLC through IDT7202 after parsing through the SJA1000 sent to TSI system.
embedded in the chip embedded PLC software based on coldwell company provide a framework of assembly language to write.
First solve using general IO to simulate IDT7202 read and write operations, the following is a read/write IDT7202 program: FIFO_FF EQU P4.
1 P4 FIFO_EF装备。
0C1_DIR EQU P3.
3C1_EN EQU P3.
2C1_WR EQU P3.
1C1_RD EQU P3.
0 FIFO_PORT EQU P1 WRITE_FIFO: MOV SFRPAGE, # 0 fh JNB FIFO_FF, WFIFO_L1 CLR C1_DIR MOV FIFO_PORT, R7 CLR C1_EN CLR C1_WR SETB C1_WR SETB C1_EN MOV R6, # 1 RET WFIFO_L1: MOV R6, # 0 RET READ_FIFO: MOV SFRPAGE, # 0 fh JNB FIFO_EF, RFIFO_L1 SETB C1_DIR CLR C1_EN CLR C1_RD MOV FIFO_PORT, # 0 FFH MOV A, FIFO_PORT SETB C1_RD SETB C1_EN MOV R6, A MOV R7, # 1 RET RFIFO_L1: MOV R7, # 0 RET in embedded PLC STEP function and SCAN function IDT7202 read from the data, each read two frames.
Data is parsed into the corresponding register D, so that you can use the data in the ladder diagram programming.
Part of the data can be written (
That allowed by the PLC to TSI direction)
In this part of the data, PLC external RAM opened up a piece of memory as the data copy, initialization time will register D and copy for the same value, in the run in STEP function and SCAN function monitoring D a copy of the register and values are the same, if different will send P89V51RD2 D register values.
4, summary EASY embedded PLC controller
based chip built fieldbus controller ETS has practical application in industrial field at present, the overall situation is good.
It should be said that EASY chip embedded PLC is a successful product.
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